1. Field of the Invention
The present invention generally relates to data transmissions between two electronic circuits. The present invention more specifically relates to the simultaneous transmission, over the same wire, of a power supply, clock, and data signal between a master circuit and one or several slave circuits.
2. Discussion of the Related Art
Communication protocols between a master circuit and a slave circuit which transmit, over the same wire, a power supply, synchronization, and data signal, are generally called single-wire protocols. Most often, the master and slave circuits further have a common voltage reference (typically the ground).
U.S. Pat. No. 5,903,607 describes a system of transmission over a single-wire bus in bidirectional mode.
FIG. 1 is a simplified block diagram of such a transmission system.
FIGS. 2A, 2B, and 2C are timing diagrams illustrating the operation of the system of FIG. 1.
A master electronic circuit 1 (MD) is connected, by a single-wire bus B, to slave circuit 3 (SD). Circuits 1 and 3 further share the same ground or more generally the same reference potential (GND). Circuit 1 (for example a processing circuit of microprocessor type) is supplied with a voltage Vcc, which is, for example, positive with respect to the ground. Circuit 3 (for example, a memory or another processing circuit) is generally not autonomously powered and draws its power supply from the transmission over the communication bus. To make the presence of a common voltage reference clearer, bus B, although considered as a single-wire bus, has been shown in the drawings as including a ground wire 4 in addition to a wire 2 over which power supply, clock, and data signal S transits. The connection to ground 4 may be functional by the rest of the elements of the circuit or of the device.
Master circuit 1 comprises output and input interfaces illustrated in FIG. 1 respectively by output and input terminals OUT and IN connected to wire S. Slave circuit 3 also comprises input and output interfaces illustrated by input and output terminals IN and OUT.
FIGS. 2A to 2C are timing diagrams illustrating a data transmission in a bidirectional mode between master circuit 1 and slave circuit 3.
FIG. 2A illustrates an example of the shape of signal SM imposed by master circuit 1. FIG. 2B illustrates the shape of a signal SS imposed by slave circuit 3 to transmit data in return. FIG. 2C illustrates the shape of resulting signal S on the bus. Signal S corresponds to the signal present on terminals IN of circuits 1 and 3. For simplification, signals SM and SS have been schematized as respectively originating from the transmission circuits of master circuit 1 and of slave circuit 3 and it is considered that the reception circuits connected to terminals IN only see the level of signal S.
Master circuit 1 modulates signal SM in amplitude between two levels V1 and V0, for example, both positive, according to a predefined coding. In fact, circuit 1 modulates at the rate of a clock the pulse widths at level V1 according to the state of the bit to be transmitted. The slave circuit draws its power supply from a filtering at the level of signal S. The quiescent level of signal S for example is level V1. In the shown example, a transmission is initialized by a start bit START in which signal SM is positioned (time t1) at a level V0 while its quiescent level is level V1. This initializes slave circuit 3 and prepares it to receive data and to transmit data in return. Master circuit 1 modulates the level of signal SM at the rate of a clock signal which sets the transmission rate and which enables the slave circuit to extract a clock for sequencing its operation and for synchronizing the transmission with the master circuit. The transmission of a bit at state 0 occurs, for example, with a pulse of level V1 of a duration shorter than the half-period of the clock signal (for example, ¼ of the period) while a state 1 is coded with a pulse of level V1 of a duration longer than the half-period of the clock signal (for example, ¾ of the period). Slave circuit 3 detects the amplitude variation and the corresponding duration of the high and low pulses to determine the value of the transmitted bits. In the direction from slave circuit 3 to master circuit 1 FIG. 2B), the slave circuit modifies the load that it imposes on wire S according to the state of the bit that it wishes to transmit. In the example of FIG. 2B, the slave circuit does not modify the load to transmit a 1 (times t2 and t3). To transmit a 0 (times t4 and t5), it pulls (times t4 and t5) signal SS to the low level, which results in decreasing the duration of the pulse of signal S. This amounts, for the slave circuit, to modulating the width of the pulses of level V1 of signal S according to the state of the bit to be transmitted. The master circuit monitors the level of signal S and, if the level that it has transmitted has not been modified, considers a response by a state 1, while when it detects a modification in the duration of the pulse with respect to the one that it transmits, it considers the reception of a state 0.
A single-wire protocol such as discussed in relation with the above drawings has a rate limited by the period of the clock signal imposed by the master circuit. Further, the master circuit can only transmit a single signal to slave circuits.